The present invention relates generally to an electrostatic discharge (ESD) protection device, and more particularly to a multi-finger ESD protection device with ballasting resistance for reducing the voltage stress on input/output pads of integrated circuits (ICs) during an ESD event.
As the feature sizes of semiconductor devices are being reduced to the nanometer level, semiconductor devices are getting more susceptible to ESD events. ICs formed of MOS (metal-oxide semiconductor) transistors are especially prone to ESD damages. A common technique to prevent ICs from being damaged by ESD events is using a multi-finger ESD protection device on the input/output pads of ICs.
A multi-finger ESD protection device is a series of transistors placed in parallel like fingers across the input/output pads of an IC so that it can have relatively large device widths to discharge ESD currents to ground potential Vss. To function properly, the trigger voltage of the multi-finger ESD protection device should be smaller than the trigger voltage of the other devices not used for ESD protection. Moreover, the multi-finger ESD protection device should not turn on during normal operation of an input/output circuit. During the conducting state, the multi-finger ESD protection device should provide a low resistance and have a high current handling capability.
A well-known problem with the multi-finger ESD protection device is the possibility of non-uniform triggering of the fingers. To ensure uniform turn-on of the multi-finger ESD protection device, an approach is to add ballasting resistors to each finger to increase the trigger voltage of the subsequently triggered finger, or to increase the substrate resistance of the MOSFET (Metal-Oxide Semiconductor Field Effect Transistors). For instance, the substrate resistance can be increased by increasing the distance of the substrate contact from the source/drain region of the MOSFET, or by increasing the P-well or N-well sheet resistance.
FIG. 1 depicts a multi-finger ESD protection device according to a conventional art. The ESD protection device is formed by NMOS (N-channel Metal-Oxide Semiconductor) multi-finger transistors placed in parallel in a driver block 100. Each finger transistor has a MOS structure with a source 120a, a drain 130a and a gate electrode 110a. Two adjacent fingers share the same source or drain regions. Triggering the first finger may propagate and trigger adjacent fingers in the driver block 100.
To increase the sheet resistance or the trigger voltage of the subsequently triggered finger, resist protective oxide (RPO) film 140a and 140b are formed on the drain regions 130a. Alternatively, the RPO films 140a can also be formed on the source region 120a. The RPO film 140a or 140b is usually applied on the I/O portion of an IC as a protection layer while forming electrical contacts to the bonding pads. During a typical salicide category of fabrication technology, a layer of RPO film is first deposited over the active area (OD). Then, a resist mask is formed over the area covered by the RPO film to protect the field effect transistor area from subsequent process steps. The RPO film in the exposed areas of the IC is then etched. The remaining RPO films function as ballasting resistance for ESD protection.
Nevertheless, there are several disadvantages with this approach. First, forming the RPO film may have an adverse influence on the yield. When wet etching is applied, the process will create undercut profiles near the edge of the resist mask, resulting in poor dimensional control and resist mask peeling and even mask lift-off. Second, the RPO area may increase the size of the drain/source region and cause the mechanical stress effect, known as LOD (Length of Oxide) effect, to each finger of the ESD protection device.
FIG. 2 depicts another ballasting resistor structure as disclosed in U.S. Pat. No. 5,721,439 that uses polysilicon strips as ballasting resistors to impose a gate delay. The ballasting resistors 203 are formed by polysilicon blockage and evenly distributed throughout the drain region 220 to provide substantially uniform diffusion resistance between the drain contact 202 and the gate electrode 201 while increasing the diffusion resistance of the drain region 220. However, the disadvantage of this structure is that the polysilicon 204 are floating gates that may create reliability issues, such as punch-through or short. Moreover, the drain region 220 with the ballasting resistors 203 is considered relatively large because they may suffer area efficiency on the input/output of an IC.
FIG. 3 shows another approach as described in U.S. Pat. No. 6,587,320, called “back-end-ballasting”. In this embodiment, the ESD ballasting is formed by a ballasting network consisting of “back-end” elements, such as contact-to-silicon, contact-to-poly and silicided polysilicon. As shown in FIG. 3, the approach uses a meandering strip 302 extending from the common terminal 301 to the drain region 303 of the ESD device 320. The meandering strip 302 creates a resistance path that connects a plurality of metallization layers M1˜M3, polysilicon layer P1 and interconnecting vias V1˜V2 to form ballasting resistance.
It is known that any additional layer or via can add resistance to the ballasting resistance. By making vertical interconnections to form back-end ballasting resistors, this approach can solve the problems induced by the LOD effects. However, the tradeoff is the increased cost and complexity in the manufacturing process due to the vertically formed resistance path.
As such, what is needed is a new structure of the multi-finger ESD protection device with the ballasting resistance that can increase area efficiency of MOS transistors in fully silicided technologies, and uniformly turn on each finger of the multi-finger ESD protection device.